Patent Literature 1 (see FIG. 30) discloses a bootstrap-type inverter circuit including n channel transistors Tr101 through Tr105. The inverter circuit of FIG. 30 is arranged as follows: When a high potential (High) is inputted to an IN terminal, the transistor Tr105 is switched ON, and VSS (Low) is supplied to an OUT terminal. When the IN terminal is set to a low potential (Low) in the above state, the transistor Tr101 is switched OFF and the transistor Tr102 is switched ON. This charges a node n to the level of “VDD−Vth” (where Vth represents the threshold of each n channel transistor). When the above charging causes a current to flow through the transistor Tr104 (that is, increases the source potential of the transistor Tr104), a bootstrap capacitor C101 pumps up the potential of the node n, so that the node n has “VDD−Vth+α”. This arrangement allows the output terminal OUT to receive a power source potential VDD (High) that is free from a threshold drop.